The invention relates to managing resources in a bus bridge.
A Peripheral Component Interconnect PCI bus, for example, may connect peripheral devices (xe2x80x9cPCI mastersxe2x80x9d) such as CD-ROM drives, graphics accelerators and sound cards to other computer system components. Each master can send transaction requests, such as read and write requests, to main memory through the PCI bus.
Requests made from a PCI master to main memory must pass through a PCI host bridge, which can only accommodate a limited number of transactions due to finite internal buffer resources. When more than one device makes a request, the PCI host bridge acts as an arbiter and grants access to one or more of the PCI masters to increase use up to the limit of its resources.
The host bridge may use round-robin arbitration to grant access to requests in its buffer in first-in, first-out (FIFO) order.
In a conventional round-robin arbitration, aggressive PCI masters may make so many requests in a short time that all the buffer resources of the host bridge may be used before other devices can make a request. Even if a device resubmits its rejected request later, the request may be rejected repeatedly if the PCI resources are not available. Thus, a PCI master might have its requests rejected indefinitely and be effectively locked out, unable to send or receive data.